Publication | Closed Access
A New Scaling Methodology For The 0.1 - 0.025/spl mu/m MOSFET
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Citations
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References
1993
Year
Device ModelingMu/m MosfetElectrical EngineeringEngineeringVlsi DesignMosfet StructureDouble Gate StructureNanoelectronicsSoi StructuresTechnology ScalingApplied PhysicsBias Temperature InstabilityNew Scaling MethodologySilicon On InsulatorMicroelectronicsSemiconductor DeviceMultiscale Modeling
In this work a MOSFET structure with an undoped ultra-thin epitaxial layer over an heavily doped substrate is compared to an uniformly doped MOS (2 x 10^18), a buried channel MOS and two SOI structures (Fig. 1). The first (SOI-S) is made of an ultra-thin undoped Si layer (10 nm) over a 50 nm thick oxide layer. The second one (SOI-D) is a double gate structure with a silicon layer 10 nm thick. Extremely shallow LDD-type source/drain profiles are adopted for all the considered structures.
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