Punch through stop layer optimization in bulk FinFETs

Abstract

Punch through leakage is a main component of off-state leakage in bulk FinFETs and it is usually suppressed by forming a punch through stop layer (PTSL). With triangular fins being used in 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> generation FinFET industrial volume production, this paper focuses on PTSL process optimization for FinFETs with triangular-shaped fins. The conditions of PTSL implantation are optimized and the sequence of PTSL formation process (before fin formation versus after fin formation) has been explored for the 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> time. The resultant n-type FinFETs (nFETs) exhibit low off-state leakage of 1.5 nA/um, steep sub-threshold slope of 66 mV/dec and outstanding DIBL which are better than that of the previously reported 22 nm FinFETs.