CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation

Abstract

This paper describes a reference-clock-free, high-time-resolution on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier (TDA) with duty-cycle compensation. A self-referenced clock with multiples of the clock period removes the necessity for a reference clock. In addition, a cascaded TDA with duty-cycle compensation improves the time resolution while maintaining the operational speed. Test chips were designed and fabricated using 65 nm and 40 nm CMOS technologies. The areas occupied by the circuits are 1350 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (with TDA, 65 nm), 490 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (without TDA, 65 nm), 470 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (with TDA, 40 nm), and 112 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (without TDA, 40 nm). Time resolutions of 31 fs (with TDA) and 2.8 ps (without TDA) were achieved. The proposed new architecture provides all-digital timing jitter measurement with fine-time-resolution measurement capability, without requiring a reference clock.