Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture - Concepedia

Concepedia

Publication | Closed Access

Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture

149

Citations

8

References

2002

Year

T. Ernst, C. Tinella, C. Raynaud, S. Cristoloveanu

Solid-State Electronics

Electrical EngineeringEngineeringElectronic EngineeringBias Temperature InstabilitySub-0.1 μMSoi MosfetsSemiconductor Device FabricationMicroelectronicsDevice ArchitectureSemiconductor Device

References

	Year	Citations

Page 1