Design of low power 4-bit flash ADC based on standard cells

Abstract

In this paper, a standard cell low power 4-bit flash analog-to-digital converter (ADC) is proposed. The converter utilizes comparators created using only logic gates for converting analog input signals to digital values. This novel flash architecture consists of several CMOS gates with inputs connected to a common input node or to one of the supply lines. Depending on the relationship between the input signal and a given gate's threshold voltage, the output will either be `0' or `1'. The comparator is followed by an encoder to convert the thermometer code to binary code. Low power consumption is achieved by switching off the unused parallel voltage comparators. The proposed ADC was implemented at the transistor level in a 180nm CMOS technology with a 1.8 V supply voltage and was simulated using Cadence Spectre simulator. Simulation results show that for the same speed, this ADC provides about 70% power reduction compared to a previously proposed design.