Cu Interconnect Limitations and Opportunities for SWNT Interconnects at the End of the Roadmap

Abstract

The historical understanding of the interconnect problem in electronics has been that the penalty due to the performance degradation of interconnects with technology scaling would be most severe for long interconnects at the global level. At the nanoscale, however, the nature of the interconnect problem changes and paves the way for new opportunities. This is because of the fact that the metal resistivity at small interconnect dimensions drastically increases due to size effects. In this paper, it is shown that the historical trend of achieving smaller interconnect latency for short local- and intermediate-level interconnects will not hold true for future technology nodes. This paper investigates new opportunities that rise as a consequence of this radical change in the nature of the interconnect problem. Contrary to the previous publications, which have indicated that individual single-wall carbon nanotube (SWNT) interconnects are too resistive for high-performance CMOS applications and must be used in bundles, this paper demonstrates that they can offer significant delay and energy-per-bit improvements in high-performance circuits at the end of the roadmap. Performances of various design scenarios that comprise one or a few parallel individual SWNT interconnects are compared against the performance of the conventional Cu/low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> interconnect technology at future technology nodes using delay, energy per bit, and energy-delay product as metrics.