High-Speed Packet Processing using Reconfigurable Computing

Abstract

Internet applications, notably streaming video, demand extremely high communication speeds in core networks, currently 100 Gbps and moving toward 400 Gbps and beyond. Data packets must be processed at these rates, presenting serious challenges for traditional computing approaches. This article presents a tool chain that maps a domain-specific packet-processing language called PX to high-performance reconfigurable-computing architectures based on field-programmable gate array (FPGA) technology. PX is a declarative language with object-oriented semantics. A customized computing architecture is generated to match the exact requirements expressed in the PX description. The architecture includes components for packet parsing and editing, and for table lookups. It is expressed in a register transfer level (RTL) description, which is then processed using standard FPGA implementation tools. The architecture is dynamically programmable via custom firmware updates when the packet-processing system is in operation. The authors illustrate the language, tool chain, and implementation results through a practical example involving a 100-Gbps OpenFlow implementation.