Split capacitor DAC mismatch calibration in successive approximation ADC

Abstract

A split capacitor DAC calibration method is proposed that a bridge capacitor larger than conventional design allows a tunable capacitor to compensate for mismatch. To guarantee proper calibration, a comparator with digital timing control offset cancellation is proposed. An 8-bit successive approximation ADC with 4b+4b split capacitor DAC calibration has been implemented in 65 nm CMOS, achieving 0.3LSB DNL and INL with 180fF input capacitance.