Study of fin-tunnel FETs with doped pocket as capacitor-less 1T DRAM

Abstract

In this work we propose and validate by experimentally calibrated simulations a silicon Tunnel FET(TFET) based capacitorless DRAM cell, implemented as a fully-depleted FinFET with CMOS compatible process. The devices have a conventional FinFET structure except for a p+ (for n-type TFET) doped pocket of length L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PKT</sub> and doping N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PKT</sub> between the intrinsic channel and the (n++) drain. This doped pocket creates a necessary condition to store holes injected from the source-to-body junction. In [1], there was a need to induce a potential well in order to store the excess charges; whereas in the present case a potential well is permanently present due to the doped pocket. The drain voltage is used as a control voltage to either fill the potential well with carriers (WRITE “1”) by attracting holes from the p++ source or repel them to empty the well of carriers (WRITE “0”). In contrast with the SOI Z-RAM® there is no need of impact ionization to create/inject the hole charge in the device body, the holes being injected by the forward-bias p+i junction, which significantly improves the device reliability. Measurements on FDSOI TFET devices as reported in [1,2] were performed at elevated temperatures and used to calibrate the non-local band-to-band (B2B) tunnelling model in Sentaurus TCAD [3]. The retention characteristics of the proposed memory cell is simulated at an elevated temperature of 85°C and is shown to be not degrading at higher temperature as is the case in conventional capacitorless DRAMs [4].