Effects of Channel Width and NH[sub 3] Plasma Passivation on Electrical Characteristics of Polysilicon Thin-Film Transistors by Pattern-Dependent Metal-Induced Lateral Crystallization

Abstract

This work studied the effects of channel width and plasma passivation on the electrical characteristics of a series of pattern-dependent metal-induced lateral crystallization (PDMILC) polysilicon thin-film transistors (poly-Si TFTs). The performance of PDMILC TFTs improves as each channel width decreasing. Further, PDMILC TFTs with plasma passivation outperforms without such passivation, resulting from the effective hydrogen passivation of the grain-boundary dangling bonds, and the pile-up of nitrogen at the SiO2/poly-Si interface. In particular, the electrical characteristics of a nanoscale TFT with ten wide split channels (M10) are superior to those of other TFTs. The former includes a higher field effect mobility of , a higher ON/OFF current ratio , a steeper subthreshold slope (SS) of , and an absence of drain-induced barrier lowering (DIBL). These findings originate from the fact that the active channels of the M10 TFT have exhibit the most poly-Si grain enhanced to reduce the grain boundary defects and the best plasma passivation. Both effects can reduce the number of defects at grain boundaries of poly-Si in active regions for high performances.