Networks on Chips: Structure and Design Methodologies

TLDR

The proliferation of hundreds or thousands of cores in next‑generation MPSoCs and CMPs demands high‑performance on‑chip interconnections, but traditional bus architectures become bottlenecks, making network‑on‑chip (NoC) designs a promising alternative. This study surveys common NoC architectures and techniques to address communication performance, power, signal integrity, and scalability challenges. It proposes a novel bidirectional NoC (BiNoC) with a dynamically self‑reconfigurable bidirectional channel to overcome bandwidth‑induced performance bottlenecks.

Abstract

The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many‐core system requires high‐performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection backbone can be an on‐chip bus or multilayer bus architecture. With the advent of many‐core architectures, the bus architecture becomes the performance bottleneck of the on‐chip interconnection framework. In contrast, network on chip (NoC) becomes a promising on‐chip communication infrastructure, which is commonly considered as an aggressive long‐term approach for on‐chip communications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Finally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self‐reconfigurable bidirectional channel is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.