Modeling and design of current balancing control in voltage-mode multiphase interleaved voltage regulators

Abstract

A current-balancing loop is often used in a voltage-mode multiphase interleaved voltage regulator (VR). It serves not only to balance the phase current but also to suppress the beat-frequency phase current oscillation in driving high-frequency dynamic loads such as recent central processing units (CPUs). In this paper, models were developed to predict the control characteristics of both the functions mentioned above. Two loop gain expressions were developed, one from the perspective of current balancing and the other from the perspective of suppressing beat-frequency oscillation. Based on the modeling results, a design guideline for current-loop compensation was proposed for balancing phase current and suppressing beat-frequency oscillation.