A Flexible Hardware Architecture for Wavelet Packet Transform With Arbitrary Tree Structure

Abstract

We present a new hardware architecture for implementing the orthogonal wavelet packet transform with an arbitrary wavelet tree. The architecture is flexible enough to accommodate an arbitrary wavelet filter and an arbitrary tree up to a certain depth. The tree structure is specified through an efficient register parameterization architecture. We provide a detailed description of the different modules and complexity estimates for the application-specified integrated circuit implementation of the proposed architecture.