Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges

TLDR

Commercial SoCs are rapidly scaling to thousands of cores, and while conventional planar NoCs suffer from high latency, power, and routing overhead, wireless links promise high‑bandwidth, single‑hop communication to alleviate these issues. The study aims to explore the design of wireless NoCs, identifying challenges and proposing emerging solutions for efficient, reliable on‑chip wireless interconnects. The authors analyze WiNoC architecture by outlining key challenges and evaluating emerging solutions for efficient, reliable wireless on‑chip interconnects.

Abstract

Current commercial systems-on-chips (SoCs) designs integrate an increasingly large number of predesigned cores and their number is predicted to increase significantly in the near future. For example, molecular-scale computing promises single or even multiple order-of-magnitude improvements in device densities. The network-on-chip (NoC) is an enabling technology for integration of large numbers of embedded cores on a single die. The existing method of implementing a NoC with planar metal interconnects is deficient due to high latency and significant power consumption arising out of long multi-hop links used in data exchange. The latency, power consumption and interconnect routing problems of conventional NoCs can be addressed by replacing or augmenting multi-hop wired paths with high-bandwidth single-hop long-range wireless links. This opens up new opportunities for detailed investigations into the design of wireless NoCs (WiNoCs) with on-chip antennas, suitable transceivers and routers. Moreover, as it is an emerging technology, the on-chip wireless links also need to overcome significant challenges pertaining to reliable integration. In this paper, we present various challenges and emerging solutions regarding the design of an efficient and reliable WiNoC architecture.