A study of the trench surface inversion problem in the trench CMOS technology

Abstract

This paper presents the results obtained in the study of the trench surface inversion problem for the CMOS technology using trench isolation. Special emphasis is put on the n-well CMOS technology where the inversion problem is most severe. Potential distribution along the trench surface is simulated using the SUPREM and GEMINI programs for different bias conditions, as well as for different impurity doping profiles and fixed charge densities (Q <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ss</inf> ). The results showed that Q <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ss</inf> along the trench surface has to be maintained at 5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> if the substrate doping concentration remains at 6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">14</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> . Higher substrate doping, lower n-well bias, and more negative substrate bias will help prevent trench surface inversion. p-well CMOS is more suitable for trench isolation due to the higher doping concentration inside the p-well. Experimental data showed that trench isolation gives no improvement in latch-up susceptibility when the trench surface is inverted.