Regarding Processors and Reconfigurable IP Cores as Services

Abstract

This paper proposes a service-oriented reconfigurable co-processing architecture. The novelty of the architecture is to apply service-oriented concepts to system on chip (SoC) design paradigms and utilizes each processor and IP core as a function unit. Regarded as abstract instructions, tasks can be scheduled to IP core for parallel execution automatically. A uniform IP reconfiguration interface is provided to allow function units replacement at run-time. Neither the applications nor the tool chains need to be redesigned after hardware reconfiguration. To evaluate the SOA concepts, we implemented a prototype on a state-of-art Virtex5 FPGA board with IP cores implemented from EEMBC DENBench. The prototype and experimental results demonstrate it can support a range of hardware accelerators in an efficient manner. Furthermore, results also depict that the architecture takes moderate silicon area affordable power consumption. We believe the SOA approach opens a new direction to combine SOA concepts with reconfigurable computing hardware architectures.