Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC

TLDR

Network‑on‑Chip architectures have emerged as a scalable, predictable interconnect for multicore SoCs, but existing designs such as the 2D OASIS mesh suffer from high power, cost, and limited throughput. The authors propose extending the 2D OASIS mesh to a 3D architecture, the 3D OASIS‑NoC, to address its power, cost, and throughput shortcomings. The 3D OASIS‑NoC builds on a 4×4 wormhole‑switched mesh with stall‑and‑go flow control, adding a third dimension to the topology. Preliminary evaluation results are presented, indicating the 3D OASIS‑NoC's potential advantages.

Abstract

During this last decade, Network-on-Chips (NoC) have been proposed as a promising solution for future systems on chip design. It offers more scalability than the shared-bus based interconnection, allows more processors to operate concurrently. Because NoC has dedicated wires, performance can be predicted. In this context, we proposed a 2D-NoC named OASIS, which is a 4×4 mesh topology design using Wormhole switching and Stall-and-Go flow control scheme. Although OASIS-NoC has its advantages over the shared-bus based systems, it has also some limitations such as high power consumption, high cost communication, and low throughput. To overcome those limitations we propose a 3D-NoC (3D OASIS-NoC) which is an extension to our 2D OASIS-NoC. In this paper we describe the 3D OASIS-NoC architecture in a fair amount of detail and present preliminary evaluation results.