Low-Power Divider Retiming in a 3–4 GHz Fractional-N PLL

Abstract

The resynchronization of a frequency divider output is routinely used in the design of low-noise phase-locked loops (PLLs) in order to remove additional phase noise and avoid modulus-dependent nonlinearity. However, metastability issues cause PLLs to fail to lock or to degrade jitter at certain synthesized frequencies. This brief proposes a novel automatic retiming circuit, which mitigates metastability issues and avoids induced noise degradation, without adding a relevant increase in power consumption. A 3-4-GHz PLL implementing this technique has been fabricated in 65-nm CMOS technology. Measured root mean square jitter below 500 fsec over the whole tuning range and added current consumption of 51 μA from a voltage supply of 1.2 V prove the effectiveness of the proposed solution.