IEEE Journal of Solid-State Circuits · 2006 · 163 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsHardware Description LanguagesLow-power DesignAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated Circuit DesignDigital Integrated CircuitsDigital Signal ProcessingMixed-signal Integrated Circuit DesignAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital Converter DesignAnalog-to-digital ConvertersCmos Analog Integrated CircuitsDigital-to-analog Converters
This paper studies the impact of segmentation on current-steering digital-to-analog converters (DACs). Segmentation may be used to improve the dynamic behavior of the converter but comes at a cost. A method for reducing the segmentation degree is given. The presented chip, a 10-bit binary-weighted current-steering DAC, has >60 dB SFDR at 250 MS/s from DC to Nyquist. At 62.5 MHz signal frequency and 250 MS/s, we operated the device in 9-bit unary, 1-bit binary-weighted mode. The obtained 60 dB SFDR in this measurement demonstrates that the binary nature of the converter did not limit the SFDR. The chip draws 4 mW from a dual 1.5 V/1.8 V supply plus load currents. The active area is less than 0.35 mm/sup 2/ in a standard 1P-5M 0.18-/spl mu/m 1.8-V CMOS process. Both INL and DNL are below 0.1 LSB.
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A Gradient-Error and Edge-Effect Tolerant Switching Scheme for a High-Accuracy DAC
J. Deveugele, Michiel Steyaert, Georges Gielen et al. · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · 2004 · 57 citations
Engineering, Computer Engineering, Electrical Engineering +13