Josephson integrated circuit process for scientific applications

Abstract

We have developed and are regularly practicing a seven mask-level Josephson integrated circuit fabrication process tailored to dc SQUID requirements and intended for SQUID studies and other scientific applications of Josephson technology. The process incorporates low capacitance Nb/Nb <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</inf> /PbAuIn edge junctions, PdAu shunt resistors, and a wiring pitch of 5 μm for the SQUID input coil level (which is PbAuIn). The junctions can be made as small as 2μm by 0.3μm, with a capacitance (including parasitics) of ∼0.14 pF. This process yields stable and reliable junctions and integrated circuits.