IEEE Journal of Solid-State Circuits · 1988 · 70 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignDynamic Power ReductionLow-power Digital Circuit DesignMixed-signal Integrated Circuit DesignTiming AnalysisAnalog-to-digital ConversionAnalog-to-digital ConvertersCmos Analog Integrated CircuitsComparator DesignComparatorsHigh-speed Cmos DesignOffset CancellationResponse Time
A dynamic latch preceded by an offset-cancelled amplifier is used in the 3- mu m CMOS comparator to obtain a response time of 43 ns. The offset-cancelled amplifier reduces the input-referred offset so that medium-resolution analog-to-digital converters (ADCs) can be built with this comparator. The use of pipelining within the comparator enables the offset cancellation to be done as the dynamic latch is enabled. Power and area are optimally distributed within the amplifier to minimize response time.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
4
A 400MSPS 8b flash AD conversion LSI
Y. Akazawa, Akira Iwata, T. Wakimoto et al. · 1987 · 45 citations
Engineering, Computer Engineering, Electrical Engineering +17
T. Tsukada, Yuichi Nakatani, E. Imaizumi et al. · 1985 · 14 citations
Engineering, Computer Engineering, Electrical Engineering +16