Hierarchical functional timing analysis

TLDR

The paper proposes a hierarchical timing analysis technique for combinational circuits under the XBDO delay model and establishes a foundation for incremental timing analysis under accurate sensitization criteria. The method first characterizes each left module with a generalized delay model, then performs topological delay analysis on the circuit composed of generalized gates that replace leaf modules, using the derived gate delay model. The hierarchical approach produces a more accurate delay model than topological analysis, is the first demonstration of feasibility under state‑of‑the‑art tight sensitization criteria, and experimental results show minimal loss of accuracy in practice.

Abstract

We propose a hierarchical timing analysis technique for combinational circuits under the tightest known sensitization criterion, the XBDO delay model. Given a hierarchical combinational circuit, a generalized delay model of each left module is characterized first. Since this timing characterization step takes into account false paths in each module, the delay model is more accurate than the one obtained by topological analysis. Then topological delay analysis is performed on the circuit composed of generalized gates replacing the leaf modules, where the “gate” delay model is the derived one. As far as the authors know, this is the first result that shows that hierarchical analysis is possible under state-of-the-art tight sensitization criteria. We demonstrate by experimental results that loss of accuracy in using the hierarchical approach is very minimal in practice. The theory developed in this paper also provides a foundation for incremental timing analysis under accurate sensitization criteria.