Thermal analysis of three-dimensional (3-D) integrated circuits (ICs)

TLDR

Chip temperature is generally limited by the heat removal capability of the packaging technology. The study examines thermal issues in 3‑D ICs through system‑level modeling of power dissipation and device‑ and package‑level heat removal, aiming to reduce chip temperature with innovative cooling technologies. The authors model power dissipation at the system level and analyze device‑ and package‑level heat removal, employing thermal vias and a copper bonding layer for 3‑D integration. 3‑D integration can reduce power dissipation by 20–25 % for comparable performance, yet higher performance may raise chip temperatures to unacceptable levels, indicating that additional cooling methods could be beneficial.

Abstract

In this paper, we examine the thermal issues in 3-D ICs by system-level modeling of power dissipation and analytical and numerical modeling of deviceand package-level heat removal. We find that for comparable system performance in 2-D and 3-D ICs, 20%-25% reduction in power dissipation can be achieved by 3-D integration due to lower capacitance associated with interconnects and clock networks. If the system performance in 3-D ICs is higher (compared to that of 2-D ICs), chip temperature could reach an unacceptable level. The chip temperature is generally limited by the heat removal capability of the packaging technology. To reduce the chip temperature in 3-D ICs for reliable operation of devices and interconnects, innovative package-level cooling technologies will be necessary. Thermal vias, Cu bonding layer for 3-D integration, etc. could also be beneficial for heat removal in 3-D ICs.