Uneven bin width digitization and a timing calibration method using cascaded PLL

Abstract

Digitizers with uneven bin widths become more practical as the calibration in digital domain becomes convenient. In order to specify and compare the measurement ability of digitizers with uneven bin widths, it is necessary to define a parameter that takes effects of the various bin widths into account. In this paper, a parameter called equivalent bin width is defined based on mechanism of digitization. A scheme for timing bin widths calibration using cascaded phase lock loop (PLL) circuits is also presented in this document.