Journal of High Speed Networks · 1992 · 46 citations · 6 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureComputer NetworksParallel ComputingHardware AccelerationNetwork-on-chip DesignParallel ArchitecturesParallel Computer ArchitectureRoutingRouting ArchitectureActive Storage ManagementChecksum AlgorithmsChecksum TechniquesException TrackingGigabit EthernetHigh-performance NetworkingNetwork-on-chip ArchitecturesPacket Processing
In this paper we illustrate the application of SWIM's Active Storage Element (ASE) module in constructing high performance IP routers. The logic associated with each ASE is a wide-instruction-word micro-programmable engine, that has been specially designed to efficiently perform operations such as pointer dereferencing, memory indirection, bounds checking, and so forth. This makes it well suited to performing operations such as parsing of the IP header, routing table lookup, checksum computation and exception processing. Our results show that a single ASE running at 20 MHz can process 400,000 packets per second: well over that required to sustain a gigabit router. Multiple ASEs can be used in parallel to achieve even higher processing rates.
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