2007 · 16 citations · 5 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsComputer ArchitectureDigital CommunicationDigital Signal ProcessingMillimeter-wave CommunicationsNetwork-on-chip DesignAdaptive EqualizationEqualizationTransceiver ArchitecturesTransceiver Design
Fabricated in 90nm CMOS, the chip consumes 545mW and has a pattern-balancing adaptive equalizer that is stable for any data patterns including those with a strong peak component at a single frequency. The adaptive equalizer yields a gain at f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> /2 relative to f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> /16 varying from -1.7 to 2.2dB for any 8B10B encoded Ethernet frames filled with a fixed data byte
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A 10Gb/s CMOS adaptive equalizer for backplane applications
Srikanth Gondi, Jri Lee, Daisuke Takeuchi et al. · 2005 · 72 citations
Engineering, Computer Engineering, Electrical Engineering +16
A CMOS multichannel 10-Gb/s transceiver
H. Takauchi, Hirotaka Tamura, Satoshi Matsubara et al. · IEEE Journal of Solid-State Circuits · 2003 · 63 citations
Engineering, Computer Engineering, Electrical Engineering +17
5-6.4 Gbps 12 channel transceiver with pre-emphasis and equalizer
H. Higashi, Masaya Kibune, Satoshi Matsubara et al. · 2004 · 15 citations