A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise

Abstract

SAR-ADC power efficiency has improved due to its digitally oriented nature that utilizes the high switching speed of nanometer CMOS processes. In recent reports, time-interleaving techniques and multi-bit-per-cycle conversion have boosted speed to the GHz sampling range at low power consumption. However, to achieve SNR of >70dB at moderate sampling speed, SARs still need a lot of power, namely tens of mW [1-2]. In [1], a very high SNR of 90dB is achieved by a stage to amplify residue charge, which is one of the reasons for the 105mW power consumption at 12.5MS/s. In [2], 8× oversampling and a static current pre-amplifier for the comparator improve SNR to 88dB, but the ADC still consumes 66mW. In [3], digital calibration achieves an SNDR of 71dB at 3mW, but double conversion limits the sampling speed to 22.5MS/s.This paper describes a SAR ADC with 71dB SNDR that runs at 50MS/s and consumes 4.2mW. The ADC uses 3 SNDR-enhancement techniques that utilize noise and that have good compatibility to low-voltage fine digital processes.