Concatenated BCH codes for NAND flash memories

Abstract

In this work, we consider designing high-rate error-control systems for storage devices using MLC NAND flash memories. Traditional systems designed with either a single BCH code or multiple short BCH codes may suffer from high decoding complexity or rate loss due to limited error-correcting capability, respectively. Aiming at achieving a stronger error-correcting capability with much reduced complexity, we propose an error-control system using a concatenation of short BCH codes with iterative decoding strategies. The performance of the proposed coding scheme is thoroughly analyzed and evaluated with computer simulations and a semi-analytic way at a target page-error rate, 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-14</sup> , which confirms our claims: the proposed coding scheme achieves good error-performance and complexity tradeoffs as compared to the traditional schemes and is very favorable for implementation.