Bias stress in organic thin-film transistors and logic gates

Abstract

Threshold voltage instabilities of all-organic thin-film transistors are investigated as a function of stress time and stress bias. The dominant effect is a positive threshold shift for negative gate bias stress which is explained by mobile ions drifting in the insulator when a gate field is applied. Trapping of charge carriers at the semiconductor–insulator interface plays only a minor role. Furthermore, we investigate the stress behavior of a basic logic element, an inverter. In comparison to a single transistor, we observe improved stability which arises from partial compensation of the parametric shifts during operation.