A 14-b linear capacitor self-trimming pipelined ADC

Abstract

The capacitor mismatch in a 1.5-b/stage pipelined ADC is background calibrated in the analog domain using a pseudorandom (PN) dithering concept. The reference voltage added/subtracted during the normal operation is used as a dither to PN-modulate the mismatch error so that it can be embedded into the residue and be recovered later by correlating with the same PN sequence. Six MSB stages are simultaneously calibrated using separate zero-forcing feedback loops. The signal-subtracted analog PN correlation shortens the calibration time by one order. A 4.2/spl times/3.8 mm/sup 2/ prototype chip in 0.18-/spl mu/m CMOS exhibits /spl plusmn/1 LSB INL at 14 b and 84 dB SFDR at 30 MS/s, and consumes 350 mW at 3 V.