IEEE Transactions on Circuits & Systems II Express Briefs · 2011 · 57 citations · 10 references
EngineeringElectrical EngineeringAnalog ElectronicsDigital CommunicationHardware Description LanguagesAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated Circuit DesignDigital Integrated CircuitsDigital Signal ProcessingMixed-signal Integrated Circuit DesignAnalog-digital ConversionAnalog-to-digital ConversionDigital-to-analog Converter DesignDigital-to-analog ConvertersInterleaved ConvertersInterleavingInterleaving TechniquesReturn-to-zero Signaling
A generalized theoretical analysis of interleaved digital-to-analog converters (DACs) is presented to explain the cancellation of image replicas. A new RF-DAC architecture comprising <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> -parallel DACs and using both clock and hold interleaving structure is proposed. The architecture is analyzed using a general mathematical model that can be extended to other types of interleaved DACs. Additional benefits of the proposed architecture, including bandwidth and resolution enhancements, are investigated. The model is extended to analyze return-to-zero variants of this architecture with a variable hold time period. The effect of different path mismatches is further examined.
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