IEEE Journal of Solid-State Circuits · 2005 · 18 citations · 12 references
EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsAnalog IntegrationCmos Circuit DesignDigital Signal ProcessingMixed-signal Integrated Circuit DesignMixed-signal IntegrationAnalog Filter DesignCmos Analog Circuit DesignCmos Analog Integrated CircuitsEqualizationHard Disk DrivesProcessing LatencyViterbi AlgorithmViterbi Decoding
A 1 GHz CMOS analog front-end for general partial response maximum likelihood (GPRML) read channel in hard disk drive application has been implemented in 0.35 /spl mu/m CMOS. A continuous time analog filter fulfills the relaxed equalization for GPRML detection and can save up to 35% power consumption for the whole read channel. An analog DFE-based timing recovery loop is implemented to avoid the extremely long latency in the digital signal processing path (Viterbi decoder). The measured performances is 1.1 dB off simulations at 800 MHz and 1.6 dB off at 1GHz. The chip draws 240 mW from a 3.3 V supply at 800MHz clock and 380 mW from a 3.6 V supply at 1 GHz clock.
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Analog MOS integrated circuits for signal processing
A.S. Sedra · Proceedings of the IEEE · 1987 · 761 citations