A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65nm CMOS

Abstract

An 11b asynchronous successive approximation register analog to digital converter with embedded passive gain architecture is proposed and prototyped in 65nm CMOS. The proposed passive gain technique is integrated in the sampling capacitor network as part of the SAR conversion, and provides a signal gain of 2x prior to the comparator without consuming static current. It thus reduces the comparator noise impact as well as enhancing the overall ADC conversion speed and power efficiency. The ADC prototype demonstrates a peak SNDR of 63.1dB and SFDR of 75.2dB when sampling at 95MS/s. Both measured differential and integral nonlinearities of the prototype are less than 0.84 LSB. It occupies an active area of 0.073mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and dissipates 1.36mW from 1.1V supply.