8.4 A 28Gb/s 1pJ/b shared-inductor optical receiver with 56% chip-area reduction in 28nm CMOS

Abstract

Next-generation high-performance computing systems require high-bandwidth serial links to transport high-speed data streams among computational blocks. Optical links have recently attracted attention due to their low channel loss at high frequencies, requiring simpler equalization circuits than electrical links. The energy-efficiency of optical links can thus be significantly improved [1-5]. Broadband techniques such as inductive peaking are commonly used in highspeed optical transceivers for bandwidth enhancement at the expense of the chip area. Inductor-less receivers have been proposed [4,6] to reduce chip area but they usually consume more power or have lower data rates at given technology nodes. In this paper, we present two optical receivers that each consists of a pseudodifferential CMOS push-pull transimpedance amplifier (TIA), a DC offset-cancellation circuit, a limiting amplifier (LA) with interleaving active-feedback [6], and a T-Coil fT-doubler output buffer. The block diagram and experimental setup are shown in Fig. 8.4.1. The capacitance of the off-chip GaAs PIN photodetector (PD), which is wire-bonded to the CMOS receiver, is 100fF with 0.4A/W responsivity. The two optical receivers have identical designs except for the LA, in which two different inductive peaking techniques, conventional and shared-inductor, are designed and fabricated on the same die in 28nm CMOS technology.