Relative timing [asynchronous design]

TLDR

Relative timing (RT) is a method for asynchronous design. RT makes timing requirements explicit and allows them to be added, removed, and optimized directly. RT synthesis and verification on three example circuits demonstrate up to three‑fold improvements in performance, area, power, and testability, and serve as the foundation for optimized timed designs in an industrial test chip that could be formalized and automated.

Abstract

Relative timing (RT) is introduced as a method for asynchronous design. Timing requirements of a circuit are made explicit using relative timing. Timing can be directly added, removed, and optimized using this style. RT synthesis and verification are demonstrated on three example circuits, facilitating transformations from speed-independent circuits to burst-mode and pulse-mode circuits. Relative timing enables improved performance, area, power, and functional testability of up to a factor of 3/spl times/ in all three cases. This method is the foundation of optimized timed circuit designs used in an industrial test chip, and may be formalized and automated.