2008 · 80 citations · 1 references
EngineeringElectrical EngineeringMaterials ScienceElectronic MaterialsMicroelectronicsSemiconductor DevicesCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyDevice ScalingIntegrated Circuit DesignMemory DevicesMetal-oxide-semiconductor Field-effect TransistorsJunction Leakage CurrentLeakageLeakage Current ReductionMemory Cell DesignMemory Circuit DesignNon-volatile Memory DesignScalabilitySource-drain Leakage
This paper presents a capacitor-less 1T DRAM cell transistor with high scalability and long retention time. It adopts gate to source/drain non-overlap structure to suppress junction leakage, which results in 80 ms retention time at 85degC with gate length of 55 nm. Compared to the previous reports, proposed cell transistor shows twice longer retention time even though the gate length shrinks to the half of them. By TCAD analysis, we have confirmed that the improvements are attributed to the superiority of the proposed device structure.
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