ACTAS: An Accurate Timing Analysis System for VLSI

Abstract

This paper describes a timing analysis system (ACTAS: ACcurate Timing Analysis System). This system analyzes the logical behaviors of VLSI. It verifies timings at flip-flops and detects timing errors. Then, it calculates path delays of the partial combinational circuits generating the errors. If they do not satisfy timing constraints, the system detects error paths. In this system, the former method based on behavior analysis is called DYNAMIC TIMING ANALYSIS and the latter method based on path analysis is called STATIC TIMING ANALYSIS. By use of this system, it improves the timing analysis efficiency of the complicated timing of VLSI.