Compact low voltage four quadrant CMOS currentmultiplier

Abstract

A new compact low voltage four quadrant current mode CMOS multiplier is presented. Post layout simulation in a CMOS 0.5 µm technology shows a linearity error lower than 0.9% for signal swings up to ±50 µA. The circuit operates at a supply of ±1.5 V, has a static power dissipation of 0.6 mW and a 1 dB bandwidth of 33 MHz.