Single event upset immune latch circuit design using C-element

Abstract

Downscaling trend in CMOS technology on the one hand and reducing supply voltage of the circuits on the other hand, make devices more susceptive to soft errors such as SEU. Latch circuits are prone to be affected by SEUs. In this article, we propose a new circuit design of latch using redundancy with the aim of immunity against SEUs. According to simulation results, our design not only guaranties full immunity, but also has the advantage of occupying less area and consuming much less power and performance penalty in comparison with other SEU immune latches. The simulation results show that our solution has 65.76% reduction in power and about 50.65% reduction in propagation delay in comparison with TMR-latch.