Effect of CMOS Miniaturization on Cosmic-Ray-Induced Error Rate

Abstract

As device feature size is scaled down for Very Large Scale Integration (VLSI) and Very High Speed Integrated Circuit (VHSIC) applications, consideration must be given to potential increased vulnerabiliity to single particle induced upset (memory soft error or processor logic error) from the natural radiation environment. This paper describes a detailed computer aided modeling study to predict the effect of scaling on the single event upset rate in CMOS memory cells in the galactic cosmic ray environment typical of high altitude satellite orbits.