Design Automation Conference · 1988 · 43 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringDesign AutomationMicroelectronicsVlsi DesignCmos Circuit DesignIntegrated Circuit DesignLayout DesignLayout OptimizationPhysical DesignVery-large-scale Integration LayoutDevice OptimizationLayout TechniquesPlacement Algorithms
This paper describes SOLO, a program for mapping arbitrary MOS circuit schematics into efficient corresponding layouts. SOLO employs a layout strategy which allows it to be applied to circuits with sized transistors as well as to circuits which include unequal numbers of n-MOS and p-MOS transistors. The program can effectively be applied to module-size circuits including up to roughly 200 transistors.
4
Optimal Layout of CMOS Functional Arrays
Uehara, vanCleemput · IEEE Transactions on Computers · 1981 · 272 citations
Engineering, Computer Engineering, Electrical Engineering +17