26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS

Abstract

A wide range of memory configurations exist in today's high-speed digital systems to meet platform-specific bandwidth, power, capacity, and cost constraints. In the near term, DDR4 and GDDR5 are expected to meet the needs of server, client, graphics and mobile platforms [1]. Differential signaling with high-speed serial I/O enhancements will potentially continue I/O performance scaling for post-DDR4 and future buffered memory solutions. A unified memory interface that can meet the signaling requirements of all these memory standards offers several benefits: reduced cost and design time, greater platform design flexibility, and a smoother transition from DDR4/GDDR5 to a high-speed differential memory interface [2]. This paper presents a dual-mode TX that supports single-ended (SE) 1.2V-DDR4/1.5V-GDDR5 (hereafter referred to as DDR-mode) as well as high-speed differential signaling (hereafter referred to as HSD-mode), which is implemented using only thin-gate-oxide devices in 22nm CMOS. Other key design features include: (a) a DDR4/GDDR5 driver implemented using only active devices (no linearizing resistors), (b) enhanced voltage-mode driver supply regulation, (c) reconfigurable logic to support pre-emphasis in both TX modes, and (d) low-overhead digital clock-calibration techniques based on asynchronous digital sampling (ADS) to improve calibration coverage and accuracy.