Experimental study on current gain of BSIT

Abstract

A means to improve the current gain h <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FS</inf> of the BSIT in a high drain current region has been derived from an experimental study about the dependency of the h <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FS</inf> versus drain current relationship on the channel width, the gate junction depth, and the impurity concentration in the n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> high-resistivity drain region. The BSIT, designed in this manner and including 9000 channels in a chip of 7 × 10 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , exhibits a current gain over 100 and high switching speeds, a rise time of 200 ns, a storage time of 200 ns and a fall time of 25 ns at a drain current of 50 A.