A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation

Abstract

A 3.6 GHz digital fractional-N PLL combines a 4b TDC with digital element shuffling, and a 4b feedback phase interpolator with digital cancellation of mismatches. It achieves maximum in-band fractional spur of -57 dBc and in-band noise of -104 dBc/Hz at 400 kHz offset with 3 MHz bandwidth. The PLL draws 67 mA from a 1.2 V supply and occupies an active area of 0.4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 6 nm CMOS.