A small footprint interleaved multithreaded processor for embedded systems

Abstract

With the increase in the design complexity of MPSoC architectures and the need for more transistor/energy efficient processor architectures, designers are exploiting the parallelism at the thread level (TLP) through the implementation of embedded multithreaded processors. Moreover, future manycore architectures tend to use small footprint RISC cores. In this paper, we present a small footprint, scalar, in-order, 5-stage pipeline, interleaved multithreaded processor with 2 hardware thread contexts for embedded systems and SoC integration. Synthesis results in 40 nm TSMC shows that the multithreaded core area is only 19800 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 13.97 kilogates, which is almost equal to a 4KB direct mapped cache memory according to CACTI 6.5 tool [1]. The IMT core has an augmentation of 73.2% in core area compared to the monothreaded core. The multithreaded core is validated by running a simple bubble-sort application and varying the L1 D$ memory. The average performance gain is 17% compared to the monothreaded core.