Integrated tapped MOS analogue delay line using switched capacitor technique

Abstract

A tapped MOS analogue delay line based on the switched capacitor technique for realisation of low-power analogue LSIs is fabricated using a VLSI process. Excellent characteristics such as large signal handling capability, low total harmonic distortion of −85 dB for 3V(p-p) input and fast operation speed of more than 1 MHz clock rate with negligible charge transfer loss are obtained.