Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops

Abstract

Chip production yield of 70% can be increased to 91 % by using fine-grain redundant logic in which only the defective portion of the main circuit is switched to a redundant subcircuit block. In addition, defect-prediction flip-flops prevent over 80% of in-field failures caused by latent defects, while maintaining correct operation. All flip-flops are connected via a scan chain, which can be employed to reproduce states used in avoiding defects, and to trace defect points.