1K bit bubble lattice storage device: Initial tests

Abstract

All elements required for writing, storing, and reading information in a bubble lattice device have been designed and fabricated in a single test chip. Design considerations and operating margins are given for the five major components of the device: (1) write station (nucleation and wall state control in an isolated-bubble region); (2) read station (wall state discrimination and bubble detection in an isolated-bubble region); (3) storage (confinement and translation of a close-packed hexagonal bubble lattice); (4) isolated-bubble to bubble lattice transition; and (5) bubble lattice to isolated-bubble transition. All functions have been demonstrated on a single test device operating in a data-in, data-out mode. Initial error rates and sources of errors are discussed.