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Hybrid dual-threshold design techniques for high-performance processors with low-power features
14
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1997
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EngineeringVlsi DesignBox 660199Power Optimization (Eda)Computer ArchitectureSystem-level DesignPower OptimizationHardware SystemsHardware SecurityLow-power FeaturesTexasview ProfileParallel ComputingInstrumentationManycore ProcessorPower-aware DesignElectrical EngineeringComputer EngineeringMicroelectronicsLow Power ElectronicsLow-power ElectronicsCircuit Design
Article Free Access Share on Hybrid dual-threshold design techniques for high-performance processors with low-power features Authors: Uming Ko Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, Texas Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, TexasView Profile , Andrew Pua Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, Texas Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, TexasView Profile , Anthony Hill Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, Texas Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, TexasView Profile , Pranjal Srivastava Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, Texas Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, TexasView Profile Authors Info & Claims ISLPED '97: Proceedings of the 1997 international symposium on Low power electronics and designAugust 1997 Pages 307–311https://doi.org/10.1145/263272.263362Published:01 August 1997Publication History 11citation116DownloadsMetricsTotal Citations11Total Downloads116Last 12 Months10Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF
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