IEEE Transactions on Circuits & Systems II Express Briefs · 2013 · 53 citations · 20 references
EngineeringComputer EngineeringElectrical EngineeringDesign OptimizationLow-power DesignMicroelectronicsDigital Signal ProcessingHardware AccelerationLow-power Digital Circuit DesignOptimization-based DesignPower OptimizationPower-aware DesignArea-efficient DesignBit-width OptimizationBitwidth OptimizationFilter OrderHardware ResourcesMultiplier DesignMultipliersQuantization
Low-cost finite impulse response (FIR) designs are presented using the concept of faithfully rounded truncated multipliers. We jointly consider the optimization of bit width and hardware resources without sacrificing the frequency response and output signal precision. Nonuniform coefficient quantization with proper filter order is proposed to minimize total area cost. Multiple constant multiplication/accumulation in a direct FIR structure is implemented using an improved version of truncated multipliers. Comparisons with previous FIR design approaches show that the proposed designs achieve the best area and power results.
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